Skip to main content
Numerical Methods for PDEs
NumPDE
Numerical Methods for PDEs
Main navigation
Home
People
All Profiles
Principal Investigators
Postdoctoral Fellows
Students
Former Members
Events
All Events
Events Calendar
News
About
Activities
Slides
NumPDE Workshop 2025
CAMWA 50
POEMS 2026
chaotic-based block
Hardware Realization of Chaos Based Block Cipher for Image Encryption
1 min read ·
Wed, Apr 27 2011
News
chaotic-based block
Hardware
Circuits
Mohamed L. Barakat, et al., "Hardware realization of chaos based block cipher for image encryption." In ICM 2011 Proceeding, 2011, 1. Unlike stream ciphers, block ciphers are very essential for parallel processing applications. In this paper, the first hardware realization of chaotic-based block cipher is proposed for image encryption applications. The proposed system is tested for known cryptanalysis attacks and for different block sizes. When implemented on Virtex-IV, system performance showed high throughput and utilized small area. Passing successfully in all tests, our system proved to be